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> 74ABTH32543 36-bit registered widebus transceiver (X10
74ABTH32543 36-bit registered widebus transceiver (X10
36 Bit Registered Bus Transceiver
* Members of the Texas Instruments Widebus+TM Family
* State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
* Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
* Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 5 V, TA = 25 C
* High-Impedance State During Power Up and Power Down
* Released as DSCC SMD 5962-9557801NXD
* Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
* High-Drive Outputs (-32-mA IOH, 64-mA IOL)
* Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
The 'ABTH32543 are 36-bit registered transceivers that contain two sets of D-type latches for temporary storage of data flowing in either direction. These devices can be used as two 18-bit transceivers or one 36-bit transceiver. Separate latch-enable (LEAB\ or LEBA\) and output-enable (OEAB\ or OEBA\) inputs are provided for each register to permit independent control in either direction of data flow.
The A-to-B enable (CEAB\) input must be low to enter data from A or to output data from B. If CEAB\ is low and LEAB\ is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB\ puts the A latches in the storage mode. With CEAB\ and OEAB\ both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar but requires using the CEBA\, LEBA\, and OEBA\ inputs.
When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
