for 2.125 GBd serial data rates.
References to SSTL_2 in the text
will also apply to SSTL_3; however,
there are separate tables and figures
showing voltage values and connection
silicon bipolar integrated circuits in
a metallized QFP package. They
provide a low-cost physical layer
solution for 2.125 GBd serial link
interfaces including a complete
Serialize/Deserialize (Serdes) function
with transmit and receive sections
HDMP-2630/2631 are also capable
of operating on 1.0625 GBd serial
RX_RATE select the data rates on
the transmit and receive sides
As shown in Figure 1, the transmitter
parallel SSTL_2 data (TX[0:9]) and
a 106.25 MHz SSTL_2 byte clock
(TBC) and serializes them into a
parallel data is expected to be
8B/10B encoded data or equivalent.
internal to the sender. New data
TBC; this is called Double Data
between the two edges of TBC to
latch TX[0:9] data into the input
register of the transmitter section
data transitions on the falling
edge of TBC and this edge is used
to latch in parallel data resulting
in a 1.0625 GBd serial stream.
This clock is then multiplied by
serial clock for the high-speed
serial outputs. The high speed
outputs are capable of interfacing
directly to copper cables or PCB
traces for electrical transmission
module for optical transmission.
10-bit wide parallel Tx, Rx busses
Option to set Tx and Rx serial
Parallel data I/O, clocks and
control compatible with SSTL_2
Differential PECL or LVTTL REFCLK
Source synchronous clocking of
synchronous clocking of receive
Differential BLL serial I/O with
Fibre channel arbitrated loop and
