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> Lattice GAL16V8D-10LPN generic array logic E2 cmos pld
Lattice GAL16V8D-10LPN generic array logic E2 cmos pld
HIGH PERFORMANCE E2CMOS TECHNOLOGY
3.5 ns Maximum Propagation Delay
3.0 ns Maximum from Clock Input to Data Output
UltraMOS Advanced CMOS Technology
50% to 75% REDUCTION IN POWER FROM BIPOLAR
75mA Typ Icc on Low Power Device
45mA Typ Icc on Quarter Power Device
High Speed Electrical Erasure (<100ms)
EIGHT OUTPUT LOGIC MACROCELLS
Maximum Flexibility for Complex Logic Designs
Programmable Output Polarity
Also Emulates 20-pin PAL Devices with Full Function/Fuse Map/Parametric Compatibility
PRELOAD AND POWER-ON RESET OF ALL REGISTERS
High Speed Graphics Processing
Standard Logic Speed Upgrade
ELECTRONIC SIGNATURE FOR IDENTIFICATION
The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasabl (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. An important subset of the many architecture configurations possible with the GAL16V8 are the PAL architectures listed in the table of the macrocell description section. GAL16V8 devices are capable of emulating any of these PAL architectures with full function/fuse map/parametric compatibility. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.
The device is a 20-pin Dual-In-Line package.
This device IS CMOS, therefore it is static sensitive.
**FREE POSTAGE ON EACH ADDITIONAL IC**
